The present invention relates to a semiconductor memory device and, more particularly, to an address counter circuit for automatically generating addresses inside a memory in a high-speed operation mode.
Counter circuits using typical flip-flops have become an established technology. But a counter circuit used in a PBM (Pipelined Burst Mode) must fulfill the following timing condition to ensure normal operation.
If a clock signal is input to the counter circuit to cause it to count up before a start address is determined, the circuit starts counting up from a wrong start address, resulting in an operation error.
To cause the counter circuit to properly operate, therefore, the count operation of the counter circuit must be started after a lapse of a sufficient period of time necessary for a start address to be input to the circuit.
For this purpose, the timing margin until a start address is properly received by the counter circuit must be considered, in addition to the time required to count up the start address after a clock signal is input to the counter circuit.
FIG. 1 shows a T-type flip-flop which is constituted by six NAND gates 71 to 76 and serves as the core of a 1-bit counter circuit.
This T-type flip-flop operates like other common flip-flops; the output states are inverted from Q to Q and from Q to Q every time a clock pulse CK is input.
Such a T-type flip-flop, however, does not have the function of setting the initial values of outputs Q and Q, and hence cannot be used as a counter circuit. That is, this flip-flop cannot be initialized to the state of Q=H and Q=L or Q=L and Q=H.
To use this flip-flop as a counter circuit capable of initialization, two NAND gates 77 and 78, two n-channel MOS transistors 79 and 80, and two p-channel MOS transistors 81 and 82 must be added to the T-type flip-flop in FIG. 1, as shown in FIG. 2. The NAND gates 77 and 78 calculate the NANDs between a clear signal CLR and addresses A and A. The n-channel MOS transistors 79 and 80 are gate-controlled by outputs from the NAND gates 77 and 78 to discharge the outputs Q and Q to the ground potential (L). The p-channel MOS transistors 81 and 82 are gate-controlled by outputs from the NAND gates 77 and 78. When the output Q or Q is discharged to the ground potential by using the n-channel MOS transistors 79 and 80, the p-channel MOS transistors 81 and 82 serve to connect the NAND gate 75 or 76, whose output is connected to one of the n-channel MOS transistors which is to be turned off, to a power supply Vcc to activate the gate.
The counter circuit having the arrangement shown in FIG. 2 operates as follows.
The clear signal CLR (pulse signal) is input to the circuit at a certain count start timing to receive a start address. Note that the clear signal CLR is a signal indicating the timing at which a count-up operation is started.
When the clear signal CLR is input, the addresses A and A are set to the outputs Q and Q. If, for example, the clear signal CLR is input when A=L and A=H, an output from the NAND gate 77 is set at H level. As a result, the n-channel MOS transistor 79 on the output Q side is turned on to set the output Q at L level. At this time, since the p-channel MOS transistor 81 is turned off, the NAND gate 75 does not operate.
An output from the NAND gate 78 is set at L level. As a result, the n-channel MOS transistor 80 on the output Q side is turned off, but the p-channel MOS transistor 82 is turned on. The NAND gate 76 is therefore activated.
In this case, since the output Q (L) is input to the NAND gate 76, the output of the NAND gate 76, i.e., the output Q, is set at H level. Thereafter, every time the clock pulse CK is input, the previous states are sequentially inverted.
Recently, demands have arisen for a synchronous memory having a burst function. Conventional memories receive an address in the first cycle and read or write data corresponding to the address in the next cycle. In contrast to this, in a memory having a burst function, a so-called burst address is set. When a burst mode is set, a burst address obtained by incrementing an address received at the start of a burst period is automatically generated to continuously read or write 2- or 4-length data corresponding to the address. In this interval, no new external address is received.
FIG. 3 shows a conventional address counter circuit constituted by two counter circuits each identical to the one shown in FIG. 2.
This address counter circuit generates 2-bit addresses Q0, Q0, Q1, and Q1. More specifically, an input address A0 at the first bit and a clear signal CLR are input to a NAND gate 77 in a first-stage counter circuit C1, and an input address A0 at the first bit and the clear signal CLR are input to a NAND gate 78.
First bits Q0 and Q0 of the burst addresses are respectively output from NAND gates 75 and 76 in the first-stage counter circuit C1. An input address A1 at the second bit and an inverted signal of the output of a NAND gate 73 in the first-stage counter circuit C1 are input to the NAND gate 77 in a second-stage counter circuit C2. An address A1 at the second bit and an inverted signal of the output of the NAND gate 73 in the first-stage counter circuit C1 are input to the NAND gate 78.
Second bits Q1 and Q1 of the burst addresses are respectively output from the NAND gates 75 and 76 in the second-stage counter circuit C2.
Assume that in a memory required to operate at a cycle time of about 15 ns to 20 ns, about 15% of the cycle time is assigned to the address counter circuit. In this case, the address counter circuit need only operate at 2.25 ns to 3 ns. In this case, an address counter circuit like the one shown in FIG. 3 suffices.
Recently, however, demands have arisen for a fast cache memory with a cycle time of about 5 ns. In this case, the time assigned to the address counter circuit must be set within 0.75 ns.
In the conventional address counter circuit shown in FIG. 3, if the input timing of a clock pulse is set to be earlier than the proper reception timing of the start address to forcibly quicken the start of operation, counting is started from a wrong start address, resulting in an operation error. For this reason, the address counter circuit must be started after a lapse of a sufficient period of time necessary for a start address to be input to the address counter circuit. In this case, however, since an excessively long period of time is required for the address counter circuit, the time assigned to the address counter circuit exceeds a cycle time of 5 ns.